Samsung Intros New Foundry Process Roadmap With 4nm Tech

Samsung Electronics on Wednesday announced a new technology roadmap for its foundry process, detailing what its future clients can expect from the company's chipmaking division in the future. The roadmap includes 4nm process tech and a number of other solutions aimed at assisting fabless and IDM semiconductor companies in making chips that are more powerful and less power-hungry. The South Korean tech giant announced six new solutions in total, including a new variant of the FD-SOI planar process technology.

The 8nm Low Power Plus (8LPP) technology is said to be an improvement over the 10LPP process that the company announced earlier this year, providing Samsung's clients with a scalable and efficient solution without employing extreme ultraviolet (EUV) lithography, the company said. On the other hand, the 7nm Low Power Plus (7LPP) is an EUV lithography-based solution that Samsung co-developed with ASML, a Dutch provider of photolithography systems. Due to the implementation of a new lithography technique, Samsung claims this tech will break Moore's law scaling in the near future, which some industry watchers believe will happen by 2021. The Seoul-based tech giant also outlined the 6nm Low Power Plus (6LPP) process that it revealed will be powered by the company's proprietary Smart Scaling technology integrated into the aforementioned 7LPP, while the 5nm Low Power Plus (5LPP) is said to be even more scalable and efficient and will serve as the ultimate solution based on the current generation of device architecture.

The jump to a new device architecture will happen with the 4nm Low Power Plus (4LPP) tech that will utilize Samsung's proprietary GAAFET structure called Multi Bridge Channel FET (MBCFETTM). The technology will rely on a Nanosheet device in an effort to improve upon the older FinFET architecture and allow for even better scaling and performance, the company said. Finally, the South Korean firm also detailed its Fully Depleted – Silicon on Insulator (FD-SOI) tech, a planar process technique designed for Internet of Things (IoT) devices that the company is planning to develop as a fully featured platform with embedded Magnetic Random Access Memory. More details on the newly introduced solutions are expected to be available later this year.

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Dominik Bosnjak

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Dominik started at AndroidHeadlines in 2016 and is the Head Editor of the site today. He’s approaching his first full decade in the media industry, with his background being primarily in technology, gaming, and entertainment. These days, his focus is more on the political side of the tech game, as well as data privacy issues, with him looking at both of those through the prism of Android. Contact him at [email protected]